<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.5"/>
<title>i2stx: xi2stx_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
  $(window).load(resizeHeight);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.png"/></td>
  <td style="padding-left: 0.5em;">
   <div id="projectname">i2stx
   </div>
   <div id="projectbrief">Vitis Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.5 -->
  <div id="navrow1" class="tabs">
    <ul class="tablist">
      <li><a href="index.html"><span>Overview</span></a></li>
      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
      <li><a href="globals.html"><span>APIs</span></a></li>
      <li><a href="files.html"><span>File&#160;List</span></a></li>
    </ul>
  </div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xi2stx__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="headertitle">
<div class="title">xi2stx_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the XI2S_Transmitter device. </p>
</div></td></tr>
<tr class="memitem:ga71367f64a4d88ca4a118a76fdb9ad3c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga71367f64a4d88ca4a118a76fdb9ad3c2">XI2S_TX_CORE_VER_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:ga71367f64a4d88ca4a118a76fdb9ad3c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="group__i2stx.html#ga71367f64a4d88ca4a118a76fdb9ad3c2">More...</a><br/></td></tr>
<tr class="separator:ga71367f64a4d88ca4a118a76fdb9ad3c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8b735fda830cc26a7c58d713191b588"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac8b735fda830cc26a7c58d713191b588">XI2S_TX_CORE_CFG_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gac8b735fda830cc26a7c58d713191b588"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Configuration Register.  <a href="group__i2stx.html#gac8b735fda830cc26a7c58d713191b588">More...</a><br/></td></tr>
<tr class="separator:gac8b735fda830cc26a7c58d713191b588"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5433601a320e6d1725885e7311c0bab4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5433601a320e6d1725885e7311c0bab4">XI2S_TX_CORE_CTRL_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga5433601a320e6d1725885e7311c0bab4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Control Register.  <a href="group__i2stx.html#ga5433601a320e6d1725885e7311c0bab4">More...</a><br/></td></tr>
<tr class="separator:ga5433601a320e6d1725885e7311c0bab4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae026183d4bfda7b544050c93cc14f431"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gae026183d4bfda7b544050c93cc14f431">XI2S_TX_IRQCTRL_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:gae026183d4bfda7b544050c93cc14f431"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Control Register.  <a href="group__i2stx.html#gae026183d4bfda7b544050c93cc14f431">More...</a><br/></td></tr>
<tr class="separator:gae026183d4bfda7b544050c93cc14f431"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0727cfd1d5dd6c4dc2957d380b82878"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaf0727cfd1d5dd6c4dc2957d380b82878">XI2S_TX_IRQSTS_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:gaf0727cfd1d5dd6c4dc2957d380b82878"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__i2stx.html#gaf0727cfd1d5dd6c4dc2957d380b82878">More...</a><br/></td></tr>
<tr class="separator:gaf0727cfd1d5dd6c4dc2957d380b82878"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a514342cc0cc00eb2d5de77f1c35831"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0a514342cc0cc00eb2d5de77f1c35831">XI2S_TX_TMR_CTRL_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga0a514342cc0cc00eb2d5de77f1c35831"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S Timing Control Register.  <a href="group__i2stx.html#ga0a514342cc0cc00eb2d5de77f1c35831">More...</a><br/></td></tr>
<tr class="separator:ga0a514342cc0cc00eb2d5de77f1c35831"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab099dec92b378872d40f46d5d37bfce3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab099dec92b378872d40f46d5d37bfce3">XI2S_TX_CH01_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:gab099dec92b378872d40f46d5d37bfce3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 0/1 Control Register.  <a href="group__i2stx.html#gab099dec92b378872d40f46d5d37bfce3">More...</a><br/></td></tr>
<tr class="separator:gab099dec92b378872d40f46d5d37bfce3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14dd880ff140c74666a9cf9136379a09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga14dd880ff140c74666a9cf9136379a09">XI2S_TX_CH23_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga14dd880ff140c74666a9cf9136379a09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 2/3 Control Register.  <a href="group__i2stx.html#ga14dd880ff140c74666a9cf9136379a09">More...</a><br/></td></tr>
<tr class="separator:ga14dd880ff140c74666a9cf9136379a09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga670aa850785e57f081453ede1f4cb4e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga670aa850785e57f081453ede1f4cb4e8">XI2S_TX_CH45_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga670aa850785e57f081453ede1f4cb4e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 4/5 Control Register.  <a href="group__i2stx.html#ga670aa850785e57f081453ede1f4cb4e8">More...</a><br/></td></tr>
<tr class="separator:ga670aa850785e57f081453ede1f4cb4e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28be098b8367b7212b8a10d2738204df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga28be098b8367b7212b8a10d2738204df">XI2S_TX_CH67_OFFSET</a>&#160;&#160;&#160;0x3C</td></tr>
<tr class="memdesc:ga28be098b8367b7212b8a10d2738204df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Channel 6/7 Control Register.  <a href="group__i2stx.html#ga28be098b8367b7212b8a10d2738204df">More...</a><br/></td></tr>
<tr class="separator:ga28be098b8367b7212b8a10d2738204df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4c3299df5616dd53e12403b0c50332b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga4c3299df5616dd53e12403b0c50332b4">XI2S_TX_AES_CHSTS0_OFFSET</a>&#160;&#160;&#160;0x50</td></tr>
<tr class="memdesc:ga4c3299df5616dd53e12403b0c50332b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 0 Register.  <a href="group__i2stx.html#ga4c3299df5616dd53e12403b0c50332b4">More...</a><br/></td></tr>
<tr class="separator:ga4c3299df5616dd53e12403b0c50332b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b7803271c5d40b4131f36985ca44d7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1b7803271c5d40b4131f36985ca44d7c">XI2S_TX_AES_CHSTS1_OFFSET</a>&#160;&#160;&#160;0x54</td></tr>
<tr class="memdesc:ga1b7803271c5d40b4131f36985ca44d7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 1 Register.  <a href="group__i2stx.html#ga1b7803271c5d40b4131f36985ca44d7c">More...</a><br/></td></tr>
<tr class="separator:ga1b7803271c5d40b4131f36985ca44d7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f71faf4e090ca874ebdd6faf8d45c58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5f71faf4e090ca874ebdd6faf8d45c58">XI2S_TX_AES_CHSTS2_OFFSET</a>&#160;&#160;&#160;0x58</td></tr>
<tr class="memdesc:ga5f71faf4e090ca874ebdd6faf8d45c58"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 2 Register.  <a href="group__i2stx.html#ga5f71faf4e090ca874ebdd6faf8d45c58">More...</a><br/></td></tr>
<tr class="separator:ga5f71faf4e090ca874ebdd6faf8d45c58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac14aa59e8a02b5bbadd089909bfe8eef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gac14aa59e8a02b5bbadd089909bfe8eef">XI2S_TX_AES_CHSTS3_OFFSET</a>&#160;&#160;&#160;0x5C</td></tr>
<tr class="memdesc:gac14aa59e8a02b5bbadd089909bfe8eef"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 3 Register.  <a href="group__i2stx.html#gac14aa59e8a02b5bbadd089909bfe8eef">More...</a><br/></td></tr>
<tr class="separator:gac14aa59e8a02b5bbadd089909bfe8eef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaecf7d1b7f8e2ea9002be176c2da7d11c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaecf7d1b7f8e2ea9002be176c2da7d11c">XI2S_TX_AES_CHSTS4_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:gaecf7d1b7f8e2ea9002be176c2da7d11c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 4 Register.  <a href="group__i2stx.html#gaecf7d1b7f8e2ea9002be176c2da7d11c">More...</a><br/></td></tr>
<tr class="separator:gaecf7d1b7f8e2ea9002be176c2da7d11c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ee4df6c437ca4892d784a41d3ac6933"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga5ee4df6c437ca4892d784a41d3ac6933">XI2S_TX_AES_CHSTS5_OFFSET</a>&#160;&#160;&#160;0x64</td></tr>
<tr class="memdesc:ga5ee4df6c437ca4892d784a41d3ac6933"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status 5 Register.  <a href="group__i2stx.html#ga5ee4df6c437ca4892d784a41d3ac6933">More...</a><br/></td></tr>
<tr class="separator:ga5ee4df6c437ca4892d784a41d3ac6933"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core Configuration Register masks and shifts</div></td></tr>
<tr class="memitem:gadd00996211fa24b4ad1fe606ac9ca68b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gadd00996211fa24b4ad1fe606ac9ca68b">XI2S_TX_REG_CFG_MSTR_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gadd00996211fa24b4ad1fe606ac9ca68b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is I2S Master bit shift.  <a href="group__i2stx.html#gadd00996211fa24b4ad1fe606ac9ca68b">More...</a><br/></td></tr>
<tr class="separator:gadd00996211fa24b4ad1fe606ac9ca68b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3791b6a3ea448f12b7430b6717251216"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga3791b6a3ea448f12b7430b6717251216">XI2S_TX_REG_CFG_MSTR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gadd00996211fa24b4ad1fe606ac9ca68b">XI2S_TX_REG_CFG_MSTR_SHIFT</a>)</td></tr>
<tr class="memdesc:ga3791b6a3ea448f12b7430b6717251216"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is I2S Master mask.  <a href="group__i2stx.html#ga3791b6a3ea448f12b7430b6717251216">More...</a><br/></td></tr>
<tr class="separator:ga3791b6a3ea448f12b7430b6717251216"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad24a8b84c1cb1bc7b5b337c9983f06ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad24a8b84c1cb1bc7b5b337c9983f06ae">XI2S_TX_REG_CFG_NUM_CH_SHIFT</a>&#160;&#160;&#160;(8)</td></tr>
<tr class="memdesc:gad24a8b84c1cb1bc7b5b337c9983f06ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels bit shift.  <a href="group__i2stx.html#gad24a8b84c1cb1bc7b5b337c9983f06ae">More...</a><br/></td></tr>
<tr class="separator:gad24a8b84c1cb1bc7b5b337c9983f06ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15244aa7ed58929e6cfa985aa0925e0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga15244aa7ed58929e6cfa985aa0925e0b">XI2S_TX_REG_CFG_NUM_CH_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_REG_CFG_NUM_CH_SHIFT)</td></tr>
<tr class="memdesc:ga15244aa7ed58929e6cfa985aa0925e0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of channels mask.  <a href="group__i2stx.html#ga15244aa7ed58929e6cfa985aa0925e0b">More...</a><br/></td></tr>
<tr class="separator:ga15244aa7ed58929e6cfa985aa0925e0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadcbb270122beea24e73bd9e054037219"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gadcbb270122beea24e73bd9e054037219">XI2S_TX_REG_CFG_DWDTH_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:gadcbb270122beea24e73bd9e054037219"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S Data Width bit shift.  <a href="group__i2stx.html#gadcbb270122beea24e73bd9e054037219">More...</a><br/></td></tr>
<tr class="separator:gadcbb270122beea24e73bd9e054037219"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4aa6c0904241a95aedc1e304b461795"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad4aa6c0904241a95aedc1e304b461795">XI2S_TX_REG_CFG_DWDTH_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gadcbb270122beea24e73bd9e054037219">XI2S_TX_REG_CFG_DWDTH_SHIFT</a>)</td></tr>
<tr class="memdesc:gad4aa6c0904241a95aedc1e304b461795"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2S Data Width mask.  <a href="group__i2stx.html#gad4aa6c0904241a95aedc1e304b461795">More...</a><br/></td></tr>
<tr class="separator:gad4aa6c0904241a95aedc1e304b461795"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core Control Register masks and shifts</div></td></tr>
<tr class="memitem:gab30f15e315f8427cbe5f70dcfc766d04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gab30f15e315f8427cbe5f70dcfc766d04">XI2S_TX_REG_CTRL_EN_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:gab30f15e315f8427cbe5f70dcfc766d04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable bit shift.  <a href="group__i2stx.html#gab30f15e315f8427cbe5f70dcfc766d04">More...</a><br/></td></tr>
<tr class="separator:gab30f15e315f8427cbe5f70dcfc766d04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b2c881b163a551e9a2e691b2efbf298"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1b2c881b163a551e9a2e691b2efbf298">XI2S_TX_REG_CTRL_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gab30f15e315f8427cbe5f70dcfc766d04">XI2S_TX_REG_CTRL_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:ga1b2c881b163a551e9a2e691b2efbf298"><td class="mdescLeft">&#160;</td><td class="mdescRight">Module Enable mask.  <a href="group__i2stx.html#ga1b2c881b163a551e9a2e691b2efbf298">More...</a><br/></td></tr>
<tr class="separator:ga1b2c881b163a551e9a2e691b2efbf298"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8c9496196c2e60b679d772a5bb94bce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaf8c9496196c2e60b679d772a5bb94bce">XI2S_TX_REG_CTRL_JFE_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:gaf8c9496196c2e60b679d772a5bb94bce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable shift.  <a href="group__i2stx.html#gaf8c9496196c2e60b679d772a5bb94bce">More...</a><br/></td></tr>
<tr class="separator:gaf8c9496196c2e60b679d772a5bb94bce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ea8f32a59f2631f40ae16a73ae81049"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1ea8f32a59f2631f40ae16a73ae81049">XI2S_TX_REG_CTRL_JFE_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaf8c9496196c2e60b679d772a5bb94bce">XI2S_TX_REG_CTRL_JFE_SHIFT</a>)</td></tr>
<tr class="memdesc:ga1ea8f32a59f2631f40ae16a73ae81049"><td class="mdescLeft">&#160;</td><td class="mdescRight">Justification Enable or Disable mask.  <a href="group__i2stx.html#ga1ea8f32a59f2631f40ae16a73ae81049">More...</a><br/></td></tr>
<tr class="separator:ga1ea8f32a59f2631f40ae16a73ae81049"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaedef85bd81cde3085348c033e9346d89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaedef85bd81cde3085348c033e9346d89">XI2S_TX_REG_CTRL_LORJF_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:gaedef85bd81cde3085348c033e9346d89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification shift.  <a href="group__i2stx.html#gaedef85bd81cde3085348c033e9346d89">More...</a><br/></td></tr>
<tr class="separator:gaedef85bd81cde3085348c033e9346d89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga079cf019c32c23a6c9d4de4a1d3f79d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga079cf019c32c23a6c9d4de4a1d3f79d7">XI2S_TX_REG_CTRL_LORJF_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gaedef85bd81cde3085348c033e9346d89">XI2S_TX_REG_CTRL_LORJF_SHIFT</a>)</td></tr>
<tr class="memdesc:ga079cf019c32c23a6c9d4de4a1d3f79d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Left or Right Justification mask.  <a href="group__i2stx.html#ga079cf019c32c23a6c9d4de4a1d3f79d7">More...</a><br/></td></tr>
<tr class="separator:ga079cf019c32c23a6c9d4de4a1d3f79d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt masks and shifts</div></td></tr>
<tr class="memitem:ga474f94f8ce6c7957980f131727cb0b78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga474f94f8ce6c7957980f131727cb0b78">XI2S_TX_INTR_AES_BLKCMPLT_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga474f94f8ce6c7957980f131727cb0b78"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt bit shift.  <a href="group__i2stx.html#ga474f94f8ce6c7957980f131727cb0b78">More...</a><br/></td></tr>
<tr class="separator:ga474f94f8ce6c7957980f131727cb0b78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3a413e9c7d1c7be7eb5c970b2b1da8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad3a413e9c7d1c7be7eb5c970b2b1da8b">XI2S_TX_INTR_AES_BLKCMPLT_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga474f94f8ce6c7957980f131727cb0b78">XI2S_TX_INTR_AES_BLKCMPLT_SHIFT</a>)</td></tr>
<tr class="memdesc:gad3a413e9c7d1c7be7eb5c970b2b1da8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Complete Interrupt mask.  <a href="group__i2stx.html#gad3a413e9c7d1c7be7eb5c970b2b1da8b">More...</a><br/></td></tr>
<tr class="separator:gad3a413e9c7d1c7be7eb5c970b2b1da8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2819f9d81091b1148adf69cae58bd75d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga2819f9d81091b1148adf69cae58bd75d">XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:ga2819f9d81091b1148adf69cae58bd75d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Synchronization Error Interrupt bit shift.  <a href="group__i2stx.html#ga2819f9d81091b1148adf69cae58bd75d">More...</a><br/></td></tr>
<tr class="separator:ga2819f9d81091b1148adf69cae58bd75d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2a8cc76d84d195679304c51c9b39076"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gad2a8cc76d84d195679304c51c9b39076">XI2S_TX_INTR_AES_BLKSYNCERR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga2819f9d81091b1148adf69cae58bd75d">XI2S_TX_INTR_AES_BLKSYNCERR_SHIFT</a>)</td></tr>
<tr class="memdesc:gad2a8cc76d84d195679304c51c9b39076"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Block Synchronization Error Interrupt mask.  <a href="group__i2stx.html#gad2a8cc76d84d195679304c51c9b39076">More...</a><br/></td></tr>
<tr class="separator:gad2a8cc76d84d195679304c51c9b39076"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f0e12e2538d1ea42f12bd8e12fb8f83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga4f0e12e2538d1ea42f12bd8e12fb8f83">XI2S_TX_INTR_AES_CHSTSUPD_SHIFT</a>&#160;&#160;&#160;(2)</td></tr>
<tr class="memdesc:ga4f0e12e2538d1ea42f12bd8e12fb8f83"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status Updated Interrupt bit shift.  <a href="group__i2stx.html#ga4f0e12e2538d1ea42f12bd8e12fb8f83">More...</a><br/></td></tr>
<tr class="separator:ga4f0e12e2538d1ea42f12bd8e12fb8f83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga957f3265c9bec698c9250d1e106795f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga957f3265c9bec698c9250d1e106795f9">XI2S_TX_INTR_AES_CHSTSUPD_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga4f0e12e2538d1ea42f12bd8e12fb8f83">XI2S_TX_INTR_AES_CHSTSUPD_SHIFT</a>)</td></tr>
<tr class="memdesc:ga957f3265c9bec698c9250d1e106795f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AES Channel Status Updated Interrupt mask.  <a href="group__i2stx.html#ga957f3265c9bec698c9250d1e106795f9">More...</a><br/></td></tr>
<tr class="separator:ga957f3265c9bec698c9250d1e106795f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbe707ac375ce43702049440e0de4099"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gacbe707ac375ce43702049440e0de4099">XI2S_TX_INTR_AUDUNDRFLW_SHIFT</a>&#160;&#160;&#160;(3)</td></tr>
<tr class="memdesc:gacbe707ac375ce43702049440e0de4099"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Underflow Detected Interrupt bit shift.  <a href="group__i2stx.html#gacbe707ac375ce43702049440e0de4099">More...</a><br/></td></tr>
<tr class="separator:gacbe707ac375ce43702049440e0de4099"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1389efbbe1bf1f0d834324564556f221"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga1389efbbe1bf1f0d834324564556f221">XI2S_TX_INTR_AUDUNDRFLW_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#gacbe707ac375ce43702049440e0de4099">XI2S_TX_INTR_AUDUNDRFLW_SHIFT</a>)</td></tr>
<tr class="memdesc:ga1389efbbe1bf1f0d834324564556f221"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Underflow Detected Interrupt mask.  <a href="group__i2stx.html#ga1389efbbe1bf1f0d834324564556f221">More...</a><br/></td></tr>
<tr class="separator:ga1389efbbe1bf1f0d834324564556f221"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0de7bad6dd089f7401c230fbae6b78a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0de7bad6dd089f7401c230fbae6b78a1">XI2S_TX_GINTR_EN_SHIFT</a>&#160;&#160;&#160;(31)</td></tr>
<tr class="memdesc:ga0de7bad6dd089f7401c230fbae6b78a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable bit shift.  <a href="group__i2stx.html#ga0de7bad6dd089f7401c230fbae6b78a1">More...</a><br/></td></tr>
<tr class="separator:ga0de7bad6dd089f7401c230fbae6b78a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafa069cfbe1276144cc6e24ead6166b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gaafa069cfbe1276144cc6e24ead6166b4">XI2S_TX_GINTR_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; <a class="el" href="group__i2stx.html#ga0de7bad6dd089f7401c230fbae6b78a1">XI2S_TX_GINTR_EN_SHIFT</a>)</td></tr>
<tr class="memdesc:gaafa069cfbe1276144cc6e24ead6166b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable mask.  <a href="group__i2stx.html#gaafa069cfbe1276144cc6e24ead6166b4">More...</a><br/></td></tr>
<tr class="separator:gaafa069cfbe1276144cc6e24ead6166b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">I2S Timing Control Register masks and shifts</div></td></tr>
<tr class="memitem:ga32c4ecf17c044ae8011084623588da27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga32c4ecf17c044ae8011084623588da27">XI2S_TX_REG_TMR_SCLKDIV_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga32c4ecf17c044ae8011084623588da27"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider bit shift.  <a href="group__i2stx.html#ga32c4ecf17c044ae8011084623588da27">More...</a><br/></td></tr>
<tr class="separator:ga32c4ecf17c044ae8011084623588da27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ad611dd66000557282ecbe330b06290"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga9ad611dd66000557282ecbe330b06290">XI2S_TX_REG_TMR_SCLKDIV_MASK</a>&#160;&#160;&#160;(0xF &lt;&lt; XI2S_TX_REG_TMR_SCLKDIV_SHIFT)</td></tr>
<tr class="memdesc:ga9ad611dd66000557282ecbe330b06290"><td class="mdescLeft">&#160;</td><td class="mdescRight">SClk Divider mask.  <a href="group__i2stx.html#ga9ad611dd66000557282ecbe330b06290">More...</a><br/></td></tr>
<tr class="separator:ga9ad611dd66000557282ecbe330b06290"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Audio Channel Control Register masks and shifts</div></td></tr>
<tr class="memitem:ga6864d0fe8ae6f1b8841192c97694f032"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga6864d0fe8ae6f1b8841192c97694f032">XI2S_TX_REG_CHCTRL_CHMUX_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ga6864d0fe8ae6f1b8841192c97694f032"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX bit shift.  <a href="group__i2stx.html#ga6864d0fe8ae6f1b8841192c97694f032">More...</a><br/></td></tr>
<tr class="separator:ga6864d0fe8ae6f1b8841192c97694f032"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f8bc951ab906c7ff8c3242794df432d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga3f8bc951ab906c7ff8c3242794df432d">XI2S_TX_REG_CHCTRL_CHMUX_MASK</a>&#160;&#160;&#160;(0x7 &lt;&lt; XI2S_TX_REG_CHCTRL_CHMUX_SHIFT)</td></tr>
<tr class="memdesc:ga3f8bc951ab906c7ff8c3242794df432d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel MUX mask.  <a href="group__i2stx.html#ga3f8bc951ab906c7ff8c3242794df432d">More...</a><br/></td></tr>
<tr class="separator:ga3f8bc951ab906c7ff8c3242794df432d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:ga76cb896e1172bda01e10eb11f58e7753"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga76cb896e1172bda01e10eb11f58e7753">XI2s_Tx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ga76cb896e1172bda01e10eb11f58e7753"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="group__i2stx.html#ga76cb896e1172bda01e10eb11f58e7753">More...</a><br/></td></tr>
<tr class="separator:ga76cb896e1172bda01e10eb11f58e7753"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d0a46e656491896100303e61c472d01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga0d0a46e656491896100303e61c472d01">XI2s_Tx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ga0d0a46e656491896100303e61c472d01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="group__i2stx.html#ga0d0a46e656491896100303e61c472d01">More...</a><br/></td></tr>
<tr class="separator:ga0d0a46e656491896100303e61c472d01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga70bc2238ba573d955a77cf6752fa209a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">XI2s_Tx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__i2stx.html#ga76cb896e1172bda01e10eb11f58e7753">XI2s_Tx_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:ga70bc2238ba573d955a77cf6752fa209a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a I2S Transmitter register.  <a href="group__i2stx.html#ga70bc2238ba573d955a77cf6752fa209a">More...</a><br/></td></tr>
<tr class="separator:ga70bc2238ba573d955a77cf6752fa209a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc89f508a120762f9abfd61105622c06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">XI2s_Tx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="group__i2stx.html#ga0d0a46e656491896100303e61c472d01">XI2s_Tx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:gabc89f508a120762f9abfd61105622c06"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a I2S Transmitter register.  <a href="group__i2stx.html#gabc89f508a120762f9abfd61105622c06">More...</a><br/></td></tr>
<tr class="separator:gabc89f508a120762f9abfd61105622c06"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
	<p class="footer">&copy; Copyright 2015-2022 Xilinx, Inc. All Rights Reserved.</p>
	<p class="footer">&copy; Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.</p>
</div>
</body>
</html>
